DESIGN AND ANALYSIS OF FLOATING POINT MULTIPLICATION USING VEDIC MATHEMATICS - A REVIEW

Authors

  • Dr. Sai Venkatramana Prasada G S Srinivas University Author
  • Dr. K. Satyanarayan Reddy Srinivas University Author
  • Rashmi P C Vivekananda College of Engineering and Technology Author

Keywords:

Arithmetic algorithms, Computational efficiency, Digital signal processing, Floating-point multiplication, IEEE-754 standard, Vedic mathematics

Abstract

 Floating-point multiplication is a critical operation in digital computing and signal processing, requiring efficient and accurate methods to handle a wide range of numerical values. Traditional algorithms, such as those based on the IEEE-754 standard, offer robustness but may lack the efficiency needed for high-speed applications. This review explores the application of Vedic mathematics, an ancient Indian system of arithmetic, to the design and analysis of floating-point multiplication algorithms. By leveraging Vedic multiplication sutras (formulas), this review presents a comparative analysis with conventional methods, highlighting improvements in speed, area, and power efficiency. The paper also discusses implementation challenges and future research directions in integrating Vedic mathematics with modern computing architectures.

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Published

2026-06-05

Issue

Vol. 44 No. 6 (2026)

Section

Articles